This invention generally relates to built-in self testing of electronic circuits and, more particularly, to built-in self testing of memory circuits such as embedded memories within an integrated circuit, memories on a multichip module, or off-chip memories.
Many of today""s integrated circuit (IC) designs are a complete system on a chip (SOC) that include a processor core, multiple embedded memories, logic, I/O ports and more. Embedded memories are the densest components within a SOC, accounting for up to 90% of the chip area. Memories are also the most sensitive to manufacturing process defects, making it essential to thoroughly test them in a SOC.
Built-in self-test (BIST) has become the method of choice for testing embedded memories. To use this method, one or more BIST controllers are inserted within the SOC during the chip""s design using a software design tool. One such tool is MBIST Architect(trademark), offered by the assignee. The chip is then fabricated with the added BIST controllers. During testing of the fabricated chip, a BIST controller is instructed to supply a series of patterns to the ports of an embedded memory. These patterns, also called test algorithms, typically include but are not limited to march type and checkerboard type patterns that cause a memory to produce deterministic output data. The output data can be directly compared with the input reference data from the controller. Alternatively, the output from the memory can be compressed and checked against a reference signature provided by the controller. In either case, the comparison generates a signal indicating that the memory passed or failed the test.
Present memory BIST design tools provide a user with a number of standard test algorithms for use in a BIST controller. The standard test algorithms, however, are general in nature. They are not necessarily optimal for a user""s novel or proprietary memory design. Yet with present BIST design tools, a user cannot modify or add to the standard test algorithms provided by the tool to meet specific needs.
It would be advantageous to provide a user with the ability to define its own BIST controller test algorithms for memory. It would also be advantageous to provide a software design tool that can accept user defined algorithms.
In accordance with the invention, a method for providing an algorithm to a BIST controller that tests memory within a circuit is disclosed. The method includes reading a description of a user defined test algorithm for a BIST controller and translating the description into an in-memory representation of the user defined algorithm. The method further includes reading a memory model selected by a user. The in-memory representation of the user-defined algorithm is associated with the selected memory model. An HDL description of a BIST controller is generated, operable to apply the user defined algorithm to a memory corresponding to the selected memory model.
In one aspect of the method, it may include generating an in-memory representation of a standard test algorithm contained within a software tool upon activation of the tool; and associating the in-memory representation of the standard algorithm with the selected memory model. In another aspect of the method, it may include, in a computer, providing user access to a description of a standard test algorithm; recording changes made by a user to a copy of the standard test algorithm description; and saving the changed copy as a user defined algorithm description.
Additionally, a method for building a standard test algorithm into a software tool that adds BIST controllers to circuits for testing memory therein is disclosed. The method includes reading a description of a standard test algorithm for a BIST controller; translating the description into an in-memory representation of the algorithm; and translating the in-memory representation of the algorithm into source code written in the language of the software tool. The algorithm source code is compiled with the tool source code, thereby producing a software tool with the test algorithm built therein.
Furthermore, a novel structure and arrangement for test algorithms is disclosed.